Photolithographic method for forming a structure in a semiconductor substrate

ABSTRACT

To form a pattern in a semiconductor substrate, a buffer layer, which is formed as a carbon layer, is produced between a photoresist layer and an antireflective layer, which is formed on the substrate. The pattern is produced in the photoresist layer by means of a lithography step, and then it is transferred to the layers arranged below in a subsequent step.

CLAIM FOR PRIORITY

This application claims priority to International Application No.PCT/DE02/04223 which was published in the German language on Jun. 5,2003, which claims the benefit of priority to German Application No. 10156 865.7-33, and filed in the German language on Nov. 20, 2001.

TECHNICAL FIELD OF THE INVENTION

The invention relates to a patterning method for semiconductortechnology in which a pattern is produced in a semiconductor substrate.

BACKGROUND OF THE INVENTION

The fabrication of semiconductor components often requires a patterningto be carried out by etching in one method step, in which the sectionswhich are to be removed are formed at least in part by a silicon oxideor silicon nitride. An example of this is the fabrication ofsemiconductor memory cells which have a trench capacitor and a selecttransistor. While the trench capacitor on one side is electricallyconnected to the select transistor by a buried strap, on the other sideof the trench capacitor an insulation region (STI, “shallow trenchisolation”) is produced, by means of which the trench capacitor iselectrically insulated from an adjacent memory cell. The STI region isproduced by means of a patterning step in which a surface section formedby a partial section of the trench capacitor which has previously beenproduced is removed. This means that not only silicon but also siliconoxide has to be etched, since the trench capacitor, in its uppersection, has an insulation collar made from silicon oxide. Since thereis generally a layer of silicon nitride at the surface of the sectionwhich is to be removed, it must therefore also be possible to etchsilicon nitride by means of the etching process.

With regard to the production of STI regions during the fabrication ofthe abovementioned memory cells, reference is made, by way of example,to German laid-open specifications DE 199 41 148 A1 and DE 199 44 012A1.

Considering the lateral dimensions of the trench capacitor, which are ofthe order of magnitude of 100-200 nm, the abovementioned process forproducing the STI region places extremely high demands on the positionalaccuracy, dimensional stability and flank steepness of the etchingprocess which is to be used, since the flank which is to be produced onthe recess which is to be etched has to be located with an extremely lowlateral positioning inaccuracy within the trench capacitor on the sideremote from the buried strap.

To produce ultrafine patterns on the semiconductor surface and tomaintain the minimum possible variation in the features sizes across thechip, the wafer or the batch, it is necessary for the reflection oflight of the exposure wavelength at the wafer surface(photoresist-substrate interface) to be suppressed as completely aspossibly, in order to rule out disruptive interference effects. This isparticularly true of exposure wavelengths at and below 248 nm (248 nm,257 nm) on account of the increasing reflectivity of the substrates andthe increasing sensitivity of the resists which are used. Furthermore,to achieve the maximum possible depth of focus during exposure, theresist layer which is to be exposed must be as thin as possible. Toachieve the transfer of the pattern, in particular with contact holes,it is necessary for the resist layer to be completely removed in theregions produced by the photolithographic mask, in order to be able toensure exact transfer of the pattern and therefore a functionalcomponent during subsequent method steps.

During the photolithographic process, the form of the patterned resistafter exposure is partly also determined by the base. If the baseconsists of silicon-containing insulator layers which have beendeposited by plasma chemistry, for example SiO, SiON or SiN, thechemical composition of the region of these layers which is close to thesurface can have a considerable influence on the results ofphotolithography. What are known as “resist feet” may be formed,connecting otherwise separate regions of resist, so that, during thetransfer of the pattern into layers located beneath the resist, theseresist feet cannot be etched, and therefore defective circuits orcomplete failure thereof result. This problem is made worse by thereduction in the feature size used and therefore the exposure wavelengthwhich is to be used, since as a result the distance between adjacentregions of resist decreases.

EP 0 492 253 A1 describes a photographic patterning method in which twophotoresist layers are used. An upper, relatively thin photoresist layer(top resist), after patterning with a silicon-containing agent, is maderesistant to dry-etching in an oxygen plasma. In this subsequentdry-etching step, the pattern of the top resist is transferred, with theprecise dimensions of the mask used for the patterning and with verticalflanks, into a lower, relatively thick photoresist layer (bottomresist). On account of the chemical amplification of the patterned topresist, this method has become known as CARL (chemical amplification ofresist lines). The bottom resist serves as the actual mask during theetching of the substrate. The bottom resist itself then has to beremoved in a special etching process, for example using O₂ of SO₂.Particularly during the etching of contact holes with very high aspectratios, photoresist masks of this type have the major drawback that thepolymers which are formed from the resist during the etching cannot becontrolled. Consequently, the problem of the formation of the “resistfeet” which has been outlined above can only be solved to a limitedextent, since, with very small features, this leads to a considerablereduction of the etching process window, with the result that in thiscase, too, residues of resist (“resist feet”) remain on the substratelayer which is to be uncovered, and as a result at least partiallyprevent the pattern from being transferred into the substrate insubsequent process steps, and consequently the operational reliabilityof the component is no longer ensured.

Moreover, in the known prior art, a silicon-containing insulator layer,which is generally deposited by plasma chemistry, is produced between asemiconductor substrate and a photoresist layer. As a result of theexposure of the photoresist layer, an acid is formed in this resistlayer. On account of the relatively high diffusion coefficient, thisacid is active in virtually the entire region of the exposed resistlayer, and the resist is readily soluble. On account of their chemicalcomposition, the abovementioned layers below the resist layer can act asbases, and neutralise the acid formed in the resist layer in thetransition region between the resist layer and the insulator layer belowit. As a result, the solubility of the resist is reduced in this regionand residues of resist remain at regions at which the insulator layer isto be uncovered and the resist layer is to be removed. These residues ofresist reduce the width of the window for the region of the insulatorlayer which is actually to be opened up, and, in the case of smallfeatures, may even remain in place in such a manner that the insulatorlayer is still completely covered with a thin film of resist in theregions in which it is to be uncovered even after the exposure has takenplace. This problem is made worse by the reduction in the feature sizeused and the exposure wavelength used for this purpose, particularly atwavelengths below 248 nm, in particular in 248 nm or 257 nm lithography.

SUMMARY OF THE INVENTION

The invention provides a patterning method in which small features canbe formed in the semiconductor substrate with a high level of accuracyand reliability.

In one embodiment of the invention, an antireflective layer is formed onthe semiconductor substrate and then forming a buffer layer on theantireflective layer. The photoresist layer, which is exposed by aphotolithography step so that a pattern is formed in the photoresistlayer, is deposited on this buffer layer. In a further method step, thispattern is transferred into the layers below, which at least include thebuffer layer, the antireflective layer and the semiconductor substrate.

This makes it possible to ensure that, even when very small features areto be transferred, the photoresist layer on the buffer layer below it isvirtually completely removed in the desired regions.

It is advantageous if the pattern is transferred into the layers whichlie below the photoresist layer by means of a single etching step, whichis advantageously carried out by means of an anisotropic dry-etchingprocess.

In a preferred exemplary embodiment, the buffer layer is formed as athin carbon layer. The layer thickness is advantageously less 20 nm, inparticular less than 10 nm, and preferably about 5 nm. It isadvantageous for this buffer layer to be formed by means of aplasma-enhanced deposition process, for example by means of a PECVDprocess.

The method according to the invention is particularly suitable for thefabrication of insulation regions between trench capacitors which havebeen formed in the semiconductor substrate and which, in combinationwith a select transistor, are arranged as a memory cell of a memorycomponent in a memory cell array. The regions which have been etchedclear between the trench capacitors are filled with insulating materialin order to produce the insulation regions.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the invention are explained in more detailbelow with reference to the drawings, in which:

FIGS. 1-4 illustrate the individual steps involved in the patterningmethod according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

In accordance with FIG. 1, a semiconductor substrate 1 which is to bepatterned is provided, which substrate may, for example, be a chip orwafer into which a matrix-like arrangement of trench capacitors hasalready been processed. The capacitors, in combination with in each caseone select transistor, each form a memory cell. Insulation regions,which are also known as shallow trench isolation (STI) regions, are tobe produced between the trench capacitor by means of the patterningprocess which is presented below by way of example. Since the sectionswhich are to be removed to produce the insulation regions also eachcontain partial sections of the processed trench capacitors, it isconsequently also necessary to etch silicon oxide, since the trenchcapacitors generally have an insulation collar consisting of siliconoxide.

In a subsequent method step, an antireflective layer 2 is produced onthis semiconductor substrate 1. This antireflective layer 2 may, forexample, be in the form of an organic layer, which includes an aminogroup (NH₂) at the surface, and may be applied by means of a knownspin-on technique or may be formed as a SiO, SiON or SiN layer. Duringthe exposure of the photoresist layer, this antireflective layer 2 isused to reduce fluctuations in intensity during the exposure and in thisway to prevent the photoresist from being only partially developed. Thelayer 2 is formed with a layer thickness of less than 70 nm andadvantageously with a layer thickness of approximately 45 nm.

A buffer layer, which in the exemplary embodiment is formed as a carbonlayer 3, is deposited on the antireflective layer 2 by means of aplasma-enhanced deposition process. A PECVD (plasma-enhanced chemicalvapour deposition process) may preferably be used as the depositionprocess. The carbon layer 3 can be deposited from a wide range ororganic substances. An example which may be mentioned is a process inwhich C₃H₆ with a flow rate of 600 sccm and He with a flow rate of 325sccm are introduced into a reactor in which the carbon layer 3 isdeposited from the process gases at a temperature of 550° C., a pressureof 6 torr and a high-frequency power of 800 W. However, the buffer layermay also be formed as a carbon-containing layer. It is also possible touse an HDP (high density plasma) process for deposition of the carbonlayer 3.

The carbon layer 3 is deposited with a layer thickness of less than 20nm, in particular less than 10 nm. A layer thickness of approximately 5nm has proven most advantageous for the exemplary embodiment. Ingeneral, the carbon layer 3 is to be designed to be as thin as possible,in order for the patterns produced to be transferred into the layer 1 to3 by means of a single etching step. Furthermore, keeping the carbonlayer 3 as thin as possible keeps the interfering reflections duringexposure of the photoresist layer 4 which is formed on the carbon layer3 to a low level. This photoresist layer 4 is produced from a negativeor positive resist and is exposed by conventional exposure by means of achromium mask 5.

As illustrated in FIG. 2, the regions which have been exposed in theexemplary embodiment are removed, so that resist regions 41 remain inplace on the carbon layer 3.

Then, as shown in FIG. 3, the actual process for patterning thesemiconductor substrate 1 is carried out by means of an anisotropicdry-etching step. The dry-etching step may be carried out, for example,using an O₂ plasma, by means of which the photoresist layer 4, thecarbon layer 3 and an antireflective layer 2 which has been formed fromorganic material are etched. By way of example, an F-containing and/orCl-containing etching medium can be used for the etching of an inorganicantireflective layer 2 and the substrate 1. Unetched regions of thesubstrate 1, in which, by way of example, in the application mentionedabove of the production of insulation regions, fully processed trenchcapacitors and select transistors of memory cells may be arranged,remain in place below the resist regions 41.

Finally, in one or more subsequent method steps, the resist regions 41and the patterned regions 31 of the carbon layer 3 and the patternedregions 21 of the antireflective layer 2 can be removed. The regions 31can be removed by means of a simple stripping process using an O₂plasma. The substrate 1 which has been patterned in the form of thesubstrate regions 11 is illustrated in FIG. 4.

To produce insulation regions, the regions which have been uncovered inthe substrate 1 and in the antireflective layer 2 have to be filled witha suitable insulation material in a subsequent method step, which is notshown.

The etching of the carbon layer 3 and of the layers 2 and 1 below it canadvantageously be carried out using etching media which contain Cl or F.By way of example, Cl₂, BCl₃, SiCl₄, CCl₄, CHCl₃, CF₄, CHF₃, C₂F₆, C₃F₈,C₄F₈ or SF₆ can be used.

The buffer layer 3 is not intended to be designed as a hard mask forsubsequent etching steps, but rather is used in particular to achievechemical decoupling between the photoresist layer 4 and theantireflective layer 2 and to improve and make more precise the patternprofiles in the photoresist layer 4.

The chemical interaction between the resist of the resist layer 4 andthe antireflective layer 2 on the semiconductor substrate 1 is at leastprevented by the application of the thin buffer layer as carbon orcarbon-containing layer 3 below the photoresist layer 4 to the extentthat the pattern which is to be formed in the resist layer 4 by thelithography mask is produced reliably, and scarcely any “resist feet”remain in place on the buffer layer. In general terms, this can also beachieved by forming the buffer layer as a layer whose chemicalcomposition is very similar to the chemical composition of the resistlayer 4 formed above it. In particular, it is in this case advantageousif the buffer layer does not contain any amino groups with a basicaction.

Therefore, the method according to the invention makes it possible toachieve a decoupling of chemical reactions between the photoresist layer4 and the antireflective layer 2 and in this way to achieve accurate andreproducible resolution of very small dimensions by means ofphotolithography, with the result that these very small features canalso be transferred to the substrate 1. By designing the buffer layer tobe very thin, the reflection effects are kept at a low level and,furthermore, the transfer of the pattern from the photoresist layer 4into all the layers below it can therefore be effected by means of asingle etching step.

Therefore, the thickness of the buffer layer is to be configured in sucha manner that this layer is at least sufficiently thick to allowchemical decoupling, but on the other hand has to be kept thin enough tobe able to control reflection effects and etching problems. Forming thisbuffer layer 3 also allows the complex subsequent monitoring of theresist layer 4 following the exposure operation to be significantlyreduced and further removal of material and renewed formation of theresist layer 4 and the lithography pattern which is desired therein tobe reduced, with the result that considerably cost savings can beachieved.

The method according to the invention can be used not only for STIinsulation but also for all other lithography steps involved in thefabrication of patterns in a semiconductor substrate.

1. A method for forming a pattern in a semiconductor substrate,comprising: producing an antireflective layer of an organic substance onthe semiconductor substrate; forming a buffer layer on theantireflective layer; depositing a photoresist layer on the bufferlayer; photolithographically producing a pattern in the photoresistlayer; and transferring the pattern into the antireflective layer, thebuffer layer and the semiconductor substrate arranged below thephotoresist layer.
 2. The method according to claim 1, wherein thebuffer layer is formed as a carbon layer or a carbon-containing layer.3. The method according to claim 1, wherein the buffer layer is formedwith a layer thickness of less than 20 nm.
 4. The method according toclaim 1, wherein the buffer layer is produced by a plasma-enhanceddeposition process.
 5. The method according to claim 4, wherein a PECVDprocess is used.
 6. The method according to claim 1, wherein, duringtransferring, the pattern is substantially produced by a single etchingstep.